3d heterogeneous integrations and methods of making thereof

ABSTRACT

An integrated circuit package comprising one or more electronic component(s); a first substrate including a first surface and a second surface of the first substrate; and a second substrate including a first surface and a second surface of the second substrate. The first substrate including a first first-substrate cavity on the first surface of the first substrate. The second substrate includes a first second-substrate cavity on the first surface of the second substrate. The second surface of the first substrate and the second surface of the second substrate is located between the first surface of the first substrate and the first surface of the second substrate; or the first surface of the first substrate and the first surface of the second substrate is located between the second surface of the first substrate and the second surface of the second substrate.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of priority to and is a continuationof U.S. patent application Ser. No. 17/196,721 filed Mar. 9, 2021(pending), the content of which is incorporated herein by reference inits entirety.

U.S. patent application Ser. No. 17/196,721 claims the benefit ofpriority to and is a divisional of U.S. patent application Ser. No.16/035,623 filed Jul. 14, 2018 now U.S. Pat. No. 10,964,676 (issued onMar. 30, 2021), the content of which is incorporated herein by referencein its entirety.

Application Ser. No. 16/035,623 filed Jul. 14, 2018 claims the benefitof priority to and is a continuation in part of U.S. patent applicationSer. No. 15/164,866 filed May 25, 2016 now U.S. Pat. No. 10,026,720(issued on Jul. 17, 2018), the content of which is incorporated hereinby reference in its entirety.

Application Ser. No. 15/164,866 claims the benefit of priority under 35U.S.C. § 119(e) to U.S. provisional application Ser. No. 62/166,123filed May 25, 2015 (now expired), the content of which is incorporatedherein by reference in its entirety.

Application Ser. No. 15/164,866 claims the benefit of priority to and isa continuation in part of U.S. patent application Ser. No. 14/717,798filed May 20, 2015 now U.S. Pat. No. 9,893,004 (issued on Feb. 13,2018), the content of which is incorporated herein by reference in itsentirety.

Application Ser. No. 15/164,866 claims the benefit of priority to and isa continuation in part of U.S. patent application Ser. No. 14/746,045filed Jun. 22, 2015 now U.S. Pat. No. 9,818,680 (issued on Nov. 14,2017), the content of which is incorporated herein by reference in itsentirety.

FIELD OF THE INVENTION

The subject matter herein relates to semiconductor devices and packagingof the semiconductor devices.

BACKGROUND OF THE INVENTION

As Moore's law approaches its demise and the cost per transistorincreases below the 22 nm node, device makers are pushed to seekalternative solutions to achieve higher yield, shorter interconnectlength, lower delays, lower power, smaller footprint, reduced weight andhigher performance. In a homogeneous 2.5D/3D integration approach, asingle chip is partitioned into a number of smaller chips. The smallerchips are then assembled on an interposer and wired together to form afunctional chip. In a heterogeneous 2.5D/3D integration approach, asingle chip consists of a number of circuitry blocks such as memory,logic, DSP, and RF, each separated into a smaller chip. The smallerchips can be manufactured by different foundries and can be of differentprocess nodes. The smaller chips are then assembled on an interposer andwired together to form a functional chip.

The semiconductor industry has been transitioning from a 2D monolithicapproach to a 2.5D/3D heterogeneous approach at a much slower rate thanexpected, mainly due to high costs. The high costs arise frommanufacturing, poor reliability, and low yield. Establishing a supplychain for a 2.5D/3D device depends on the device market and volume.However, costs, reliability, and yield are the fronts that are hittingthe industry the most.

A silicon interposer is the building block and an enabler for 2.5D/3Dintegration, whether homogeneous or heterogeneous. In a conventionalsilicon interposer manufacturing flow, blind vias with a diameter of 10um are created within the wafer followed by back-grinding the wafer to100 um nominal in order to reveal the vias from the backside, creatingwhat is known as through-silicon vias (TSV). Such an interposer is knownas an interposer with 10:100 aspect ratio, implying 10 um via diameterand 100 um interposer thickness. This process is called “wafer thinningand via reveal process.” In reality, not all of the blind vias areetched with equal depth, as there is always considerable variation inblind via depth due to process variation. With more than 2 um variationin blind via depth, considerable contamination occurs during theback-grind process in order to reveal all of the blind vias. In general,thinning and the via reveal process has proven to have a tremendouslynegative impact on the yield and has given the 2.5D/3D integration areputation as a costly process that is justified only if the marketdemands the technology and can absorb the associated cost.

As mentioned above, in a conventional 2.5D/3D integration and assembly,a single chip is partitioned into multiple other chips or so-calledpartitions, whether homogeneous or heterogeneous. Partitions are thenbumped using copper pillar bumping technology. Copper pillar is used forfine pitch bumping, normally when the bump pitch is less than 80 micron.A typical partition can have a bump pitch of 45 microns or smaller.Partitions are assembled on a thin silicon interposer with typicalaspect ratio of 10:100. The back side of the interposer has a typicalbump pitch of 150 micron or more in order to resemble the industrystandard flip chip bump pitch in practice as of today and is bumpedusing solder bump material. The Silicon interposer is then assembled ona multi-layer organic build up substrate. A ball grid array (BGA) with atypical pitch of 1 mm is attached to the back side of the organicsubstrate. The organic substrate is then assembled on a printed circuitboard (PCB).

The conventional silicon interposer TSV manufacturing process withsequential bumping and assemblies has resulted in a costly platformwhich has inhibited the launch of 2.5D/3D products in many marketsectors.

According to industry sources, 40% of the cost associated withmanufacturing a silicon interposer is attributed to wafer thinning andthe back-grinding via reveal process. A recent independent study shedslight on the cost break down of processing steps required formanufacturing a conventional 31×31 mm2, 100 um thin silicon interposerwith 12 um TSV diameter, 3 copper damascene RDL layers with 65 nm designrule for routing on the top layer. According to the study, 19% of thecost contribution is attributed to the wafer thinning and TSV revealprocess, 20% to wafer bonding/debonding process, 19% to TSV fillingprocess, 18% to RDL process, 13% to via etching process and only 5% tothe bumping process.

The processes related to TSVs include the wafer thinning and TSV revealprocess, the wafer bonding and debonding process, and the TSV copper viafill process. These three processes contribute to almost 60% of theoverall cost of manufacturing.

Interposers in practice today consist of redistribution layers (RDL),RDL vias, and through substrate/silicon vias (TSVs). FIG. 0A is a sideview of an assembly employing through substrate vias according to priorart. TSVs 10 are used to transition signals 20 and supplies from the top35 of the substrate 30 to the bottom 40 and vice versa through thesubstrate core thickness. TSVs are constrained by diameter, height, andpitch. Thus, a limited number of TSVs can be placed in a substrate,moreover, it has a negative impact on signal and power integrity.

BRIEF SUMMARY OF THE INVENTION

A method of creating a scalable 2.5D/3D structure without throughsubstrate vias is disclosed. The method uses a via-less semiconductorinterposer, a semiconductor substrate, and various combinations ofwirebond, flip chip bumping, and redistribution layers (RDL) totransition signals or supplies to the bottom of the substrate.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A, 1B, and 1C are side views of a stacked die structure, inaccordance with one exemplary embodiment of the present invention.

FIGS. 1E, 1F, and 1G are side views of an assembly, in accordance withone exemplary embodiment of the present invention.

FIG. 1H is a top view of the assembly shown in FIG. 1G.

FIG. 2A is a side view of an assembly, in accordance with one exemplaryembodiment of the present invention.

FIG. 2B is a side view of an assembly, in accordance with one exemplaryembodiment of the present invention.

FIG. 3A is a side view of an assembly, in accordance with one exemplaryembodiment of the present invention.

FIG. 3B is a side view of an assembly, in accordance with one exemplaryembodiment of the present invention.

FIG. 3C is a side view of an assembly, in accordance with one exemplaryembodiment of the present invention.

FIG. 4 illustrates arrangements of bump patterns used to create securedrouting in accordance with an exemplary embodiment.

FIG. 5A is a side view of an assembly, in accordance with one exemplaryembodiment of the present invention.

FIG. 5B is a side view of an assembly, in accordance with one exemplaryembodiment of the present invention.

FIGS. 6A and 6B are side views of an assembly, in accordance with oneexemplary embodiment of the present invention.

FIG. 7 is a side view of an assembly, in accordance with one exemplaryembodiment of the present invention.

FIG. 8A is a side view of an assembly, in accordance with one exemplaryembodiment of the present invention.

FIG. 8B is a side view of an assembly, in accordance with one exemplaryembodiment of the present invention.

FIG. 9 is a side view of an assembly, in accordance with one exemplaryembodiment of the present invention.

FIG. 10A is a side view of an assembly, in accordance with one exemplaryembodiment of the present invention.

FIG. 10B is a side view of an assembly, in accordance with one exemplaryembodiment of the present invention.

FIG. 11 is a cross-section of a substrate connector used to routesignals and supplies over a cavity in accordance with an exemplaryembodiment.

FIG. 12 is a cross-section of a substrate connector used to routesignals and supplies over a cavity in accordance with an exemplaryembodiment.

FIG. 13A is a bump joint assembly between two substrates according toprior art.

FIG. 13B is a bump joint assembly between a substrate and a dieaccording to prior art.

FIG. 13C is a bump joint assembly between two die according to priorart.

FIG. 14 is a top view of a landing pad used to connect components, andside view of a plurality of holes shape and depth used to enforce aconnection between components in accordance with an exemplaryembodiment.

FIG. 15A is a top view of a plurality of holes with uniform pitch, shapeand depth in accordance with an exemplary embodiment.

FIG. 15B is a top view of a plurality of holes with varying pitch, shapeand depth in accordance with an exemplary embodiment.

FIG. 16 illustrates an assembly process used to assemble mask definedcomponents and substrates without using under bump metallization (UBM)in accordance with an exemplary embodiment.

FIG. 17 illustrates an assembly process used to assemble mask definedcomponents and substrates in accordance with an exemplary embodiment.

FIG. 18A illustrates a plurality of wirebonded dies placed inside asubstrates cavity in accordance with an exemplary embodiment.

FIG. 18B illustrates a plurality of wirebonded dies placed on a copperheat spreader in accordance with an exemplary embodiment.

FIG. 19A illustrates a plurality of wirebonded dies placed side by sideinside a substrate's cavity in accordance with an exemplary embodiment.

FIG. 19B illustrates a plurality of wirebonded dies placed inside asubstrate's cavity side by side and on top of each other in accordancewith an exemplary embodiment.

FIG. 19C illustrates a plurality of wirebonded dies placed side by sideinside substrate cavities in accordance with an exemplary embodiment.

FIG. 19D illustrates a plurality of wirebonded dies placed side by sideand on top of each other inside substrate cavities in accordance with anexemplary embodiment.

DETAILED DESCRIPTION OF THE INVENTION

The various embodiments are described more fully with reference to theaccompanying drawings. These example embodiments are provided so thatthis disclosure will be thorough and complete, and will fully convey thescope of the invention to readers of this specification having knowledgein the technical field. Like numbers refer to like elements throughout.

Semiconductor packages are described which increase the density ofelectronic components within. The semiconductor package may incorporateinterposers having a multitude of redistribution layers. Relativelynarrow and laterally elongated interposers to form the indentations usedto house the electronic components. The height of the clearance may beequal to the height of the standoff interposers. The semiconductorpackage designs described herein may be used to reduce footprint, reduceprofile and increase electronic component and transistor density forsemiconductor products. The spaces and clearances may form a conduitconfigured to promote fluid flow and enhance cooling of the electroniccomponents during operation in embodiments.

In some embodiments, the semiconductor packages described herein possesscavities and/or standoff interposers (generally referred to herein asinterposer) to create spaces for a plurality of electronic components ina high density and high performance configuration. In some embodiments,the semiconductor packages described may result in a smaller footprint,lower profile, miniaturized, higher performance thermally enhanced, andmore secured packages. The packages may involve a combination ofinterposers, redistribution layers (RDL), zero-ohm links, copperpillars, solder bumps, compression bonding, and bumpless packaging. Inaddition to these techniques, cavities may be made into the interposerand/or substrate, and/or standoff interposers and secondary or sidesubstrate may be used to provide spaces (clearance) for a plurality ofelectronic components (e.g., passives, antennas, integrated circuits orchips) in embodiments. The standoff interposers and secondary or sidesubstrate may include RDL on the top and/or bottom. Standoff interposersmay be formed, for example, by bonding multiple interposers together bythermocompression bonding or another low-profile connection technique.Oxide bonding techniques or laterally shifting any standoff interposerdescribed herein enable wirebonds to be used to connect the standoffinterposer to a printed circuit board, or substrate, or an underlyinginterposer in embodiments. Generally speaking, any interposer describedherein may be shifted relative to the other interposers in the stack toallow the formation of wirebonds. The semiconductor interposer may be asilicon interposer according to embodiments.

A method of creating a scalable 2.5D/3D structure which requires no TSVsis disclosed. This method uses various combinations of wirebond, flipchip bumping, redistribution layer (RDL) with or without RDL vias totransition signals or supplies In other words, signals and supplies arerouted through the RDL layers, thus eliminating TSV usage and reducingthe cost of manufacturing and improving performance. In addition, animproved method of solder joint reliability is disclosed. Surfaces ofassemblies disclosed herein maybe be covered with a high-Z material tocreate a radiation harden component.

Electronic packages formed in the manner described herein possessimproved reliability, lower cost, and higher performance due to ashortening of electrical distance and an increase in density ofintegrated circuit mounting locations. Reliability may be improved forembodiments which use the same semiconductor (e.g., silicon) for allinterposer used to form the semiconductor package. The techniquespresented also provide improved in solder joint reliability and areduction in warpage. Warping may occur during the wafer processing andthinning of the semiconductor interposer. The second opportunity forwarping occurs during the package and assembly. The chance of warpingincreases for larger interposer lengths and package dimensions which iscurrently necessary for a variety of 2.5D/3D integration applications(e.g., networking). The vertical density of integrated circuits may beincreased which allows the horizontal area to be reduced to achieve thesame performance.

When describing all embodiments herein, “top” and “up” will be usedherein to describe portions/directions perpendicularly distal from theprinted circuit board (PCB) plan and further away from the center ofmass of the PCB in the perpendicular direction. “Vertical” will be usedto describe items aligned in the “up” direction towards the “top.” Othersimilar terms may be used whose meanings will now be clear. “Majorplanes” of objects will be defined as the plane which intersects thelargest area of an object such as an interposer. Some standoffinterposers may be “aligned” in “lines” along the longest of the threedimensions and may therefore be referred to as “linear” standoffinterposers. Electrical connections may be made between interposers(standoff or planar interposer) and the pitch of the electricalconnections may be between 1 micron and 50 micron or between 10 micronand 100 micron in some embodiments. Electrical connections betweenneighboring semiconductor interposers herein may be direct ohmiccontacts which may include direct bonding/oxide bonding or adding asmall amount of metal such as a pad. In the following it is understoodthat a substrate includes metal layers, vias and other passivecomponents used for transfer of signals.

FIG. 1A is a side view of a TSV-less (i.e., without any through siliconvias) assembly 55 (alternatively referred to herein as structure) inaccordance with an exemplary embodiment of the present invention.Assembly 55 is shown as including, in part, a semiconductor die 50mounted on a interposer 90 via a multitude of electrical signalconductors (e.g., bumps). Interporser 90 is further shown, as including,in part, one or more redistribution layers 60 (RDL), and a substrate 70.Although for simplicity only one such redistribution layer is shown inFIG. 1A, it is understood that layer 60 may include any number ofredistribution later, collectively referred to herein as aredistribution layer.

Redistribution layer(s) 60 is shown as including 5 metal layers 62, 64,65, 66, 68 used to transfer signals to and from semiconductor die 50, asdescribed further below. FIG. 1B is a side view of another substrate 94having a multitude of electrical signal conductors 99 and a cavity 96adapted to receive assembly 55 therein. FIG. 1C shows assembly 55 afterbeing disposed in cavity 94. A multitude of wirebonds (two which, namelywirebonds 97 and 98 are shown in FIG. 1C) may be used to transfersignals to and from silicon die 50 via the metal layers disposed in RDL60. Alternatively, a flip-chip substrate (not shown) may be used inplace of the wirebonds to transfer signals between silicon die 50 andsubstrate 94 over cavity 96. Although for simplicity only five metallayers are shown in redistribution layer 60, it is understood that layer60 may include any number of metal layers.

FIG. 1E is a side view of a TSV-less assembly 100 in accordance withanother exemplary embodiment of the present invention. Assembly 100 isshown as including, in part, semiconductor dies (device) 50 and 52mounted on interposer 90. Although exemplary embodiment of assembly 100is shown as including only two semiconductor devices, it is understoodthat an assembly, in accordance with embodiments of the presentinvention, may have any number of semiconductor devices.

Semiconductor device 50 is shown as communicating with other devices,such as device 52, or to receive voltage/current supplies via amultitude of electrical signal conductors 58. Likewise, semiconductordevice 52 is shown as communicating with other devices, such as device50, or to receive voltage/current supplies via a multitude of electricalsignal conductors 78. Interposer 90 is further shown, as including, inpart, one or more redistribution layers 60 (RDL), and a substrate 70.Although for simplicity only one such redistribution layer is shown inFIG. 1E, it is understood that layer 60 may include any number ofredistribution later. Redistribution layer(s) 60 is shown as including 5metal layers 62, 64, 65, 66, 68 used to transfer signals to and fromsemiconductor devices 50, 52.

FIG. 1F is a side view of a substrate 94 having a multitude ofelectrical signal conductors 99 and a cavity 96 adapted to receiveassembly 100 therein. FIG. 1G shows assembly 100 after being disposed incavity 94. A multitude of wirebonds (two which, namely wirebonds 97 and98 are shown in FIG. 1C) may be used to transfer signals to, from orbetween silicon devices 50, 52 via the metal layers disposed in RDL 60.Alternatively, a flip-chip substrate (not shown) may be used in place ofthe wirebonds to transfer signals to, from or between silicon devices50, 52 and substrate 94 over cavity 96. Although for simplicity onlyfive metal layers are shown in redistribution layer 60, it is understoodthat layer 60 may include any number of metal layers. FIG. 1H is a topview of an exemplary embodiment of assembly 100, showing devices 50 and52, top metal layers 62, wirebonds 97, 98, and bonding pads 93.

FIG. 2A shows an assembly 210 in accordance with another embodiment ofthe present invention. Devices 227, 229 together with interposer 225form an assembly 235 that corresponds to and is formed in the samemanner as assembly 100 shown in FIG. 1F. Similarly, devices 230, 240together with interposer 220 form an assembly 245 that corresponds toand is formed in the same manner as assembly 100 shown in FIG. 1F.Assemblies 235 and 245 are mounted to substrate 214 to from an assembly210. Devices 229, 227, 240 and 230 of assembly 210 are adapted tocommunicate with one another via wirebonds 250, 260 and theredistribution layers disposed in interposers 220 and 225. Electricalsignal conductors 233 (e.g., BGA) facilitate communication between thedevices disposed in assembly 210 and devices not formed on assembly 210.

FIG. 2B shows an assembly 270 in accordance with another embodiment ofthe present invention. Assembly 270 is shown, as including, in part, twoassemblies 235A and 235, each of which corresponds to assembly 235 shownin FIG. 2A. The devices disposed in assemblies 235A and 235B are adaptedto communicate with one another via wirebonds 250, 260 and theredistribution layers disposed in their respective interposers 220 and225. Electrical signal conductors 290 (e.g., BGA) facilitatecommunication between the devices disposed in assembly 270 and devicesnot formed on assembly 270. In one embodiment, substrates 275 disposedbetween assemblies 235A and 235 surrounds interposers 220 and thedevices mounted there to inhibit access to these devices. In yet anotherembodiment, substrates 275 is disposed along one of the edges ofassembly 235 to enable airflow between assemblies 235A and 235 so as toallow for heat flow and dissipation. The following embodiments of thepresent invention are similar in many aspects to those described abovewith reference to FIGS. 1A, 1B, 1C, 1D, 1E, 1F, 1G, 1H, 2A, 2B;accordingly, for simplicity and clarity, in the following and whereapplicable, only the differences between such embodiments are described.It is also understood that similar reference numbers may be used toidentify the same elements in the Figures.

FIG. 3A is a cross-section view of stacking of interposers in accordancewith an exemplary embodiment. An assembly 310 may include in partmultiple assemblies, for example one according to assembly 105 and oneaccording to assembly 210, stacked and separated using a BGA 315 havinga ball size and pitch appropriate for providing enough clearance so thatdevices of the assemblies fit and function properly. Assembly 210 hasclearance from substrate 330 due to BGA 320.

FIG. 3B is a cross-section view of stacking or interposers, using largerBGA ball sizes, in accordance with an exemplary embodiment. An assembly350 comprises stacked assemblies according to assembly 210. BGAs 340 and345 provide clearance for the stacked assemblies between one another andsubstrate 355. BGAs 340 and 345 have a larger ball size and pitch,appropriate for providing enough clearance so that devices of theassemblies fit and function properly.

FIG. 3C is a cross-section view of stacking of interposers, usingsmaller BGA ball sizes, in accordance with an exemplary embodiment. Anassembly 360 comprises stacked assemblies according to assembly 210. Thetwo assemblies are shown as separated by a thin side-substrate 380 andBGAs having smaller ball size and pitch. Larger BGA 370 providesclearance from substrate 390.

FIG. 4 illustrates arrangements of bump patterns used to mask criticalsignals and/or supplies in accordance with an exemplary embodiment. Bumppattern 420 includes in part critical signals or supplies 460 andnon-critical signals or supplies 470. According to one embodiment of theinvention, critical signal/supply bumps 460 or traces may be shieldedagainst probing or tampering by placing the critical signal or supplybumps on an inner most line of bumps, namely bumps 441-446 while thenon-critical signals or supplies 470 are placed on an outer most line ofbumps. Similarly, bump pattern 410 includes in part critical signals orsupplies 440, and non-critical signals or supplies 430, 450. Similarly,signals 451-457 are shielded from probing or tampering by placing thesesignals on innermost line of the bumps. In another embodiment of thisinvention, critical signals or supplies 440 may be positioned on a lineof bumps between the non-critical signals or supplies 430 and 450.

FIG. 5A is an exemplary embodiment of an assembly in accordance withanother exemplary embodiment of the present invention. Substrate 94 isadapted to have a cavity 95 adapted to receive assembly 100 (See FIG.1E) and cavities 520 disposed either along the periphery or oppositeedges of substrate 94 to receive bumps 538 also formed on assembly 538.Since bumps 58, 78, and 538 are fully embedded within the walls ofsubstrate 94, the signals used by devices 50 and 52 are shielded fromtampering. FIG. 5B shows various components of FIG. 5A after they havebeen assembled together to form assembly 540. FIGS. 6A and 6B arerespectively similar to FIGS. 5A and 5B except that in FIGS. 6A and 6B,bumps 538 are not placed in a cavity. FIG. 7 shows two assemblies 640(see FIG. 6B) that are stacked together but separated via substrate 710.

The assembly shown in FIG. 8B is similar to that shown in FIG. 8A exceptthat in the assembly of FIG. 8B, semiconductor devices 50, 52,interposer 90, and a portion of each of substrates 45, 48 is disposed ona copper layer 550. The remaining portions of substrates 45 and 48 aredisposed on substrates 552 and 554. Substrate 94 is disposed abovedevices 50, 52 and substrates 45, 48. Bumps 560 are used to transfersignals to or from devices 50, 52 to bumps 99 for communication withdevices external to the assembly. It is understood that transfer ofsignals between bumps 560 and 99 is facilitated through signal tracesformed in PCB or substrate 94 using vias, and the like. The assembly ofFIG. 9 is similar to that shown in FIG. 8B except that in FIG. 9wirebonds 935 are used to transfer signals between various metal layersdisposed in interposer 90 and bumps 560.

FIG. 10A is an exemplary embodiment of an assembly 1000, in accordancewith another embodiment of the present invention. Assembly 1000includes, in part, a pair of substrates 94A and 94B (each correspondingto substrate 90 as described above). Each substrate has a cavity formedon its top and bottom surfaces. For example, substrate 90A is shown asincluding a cavity 96A_(top) formed on its top surface and a cavity96A_(bottom) formed on its bottom surface. Likewise, substrate 90B isshown as including a cavity 96B_(top) formed on its top surface and acavity 96B_(bottom) formed on its bottom surface. Interposer 90A_(top)has devices 50A_(top), 52A_(top) as well as substrates 45A_(top),48A_(top) disposed thereon. Interposer 90A_(bottom) has devices50A_(bottom), 52A_(bottom) as well as substrates 45A_(bottom),48A_(bottom) disposed thereon. Interposers 90B_(top) and 90B_(bottom)have similar devices and substrates thereon as shown. Bumps 610, 620,630 and 640 together with substrates 45A_(top), 48A_(top) 45A_(bottom),48A_(bottom) are used to facilitate signal transfer between the devicesshown as well as devices external to assembly 1000. In FIG. 10 , acopper heat spreader is disposed below substrates 45A_(bottom),48A_(bottom) and devices 50A_(bottom) and 52A_(bottom). It is understoodhowever, that a copper hear spreader may be disposed in other layers.

FIG. 10B illustrates stacking and scaling up low profile thermallyenhanced and secured interconnects in accordance with an exemplaryembodiment. In this example, there are no cavities in the substrate1050, instead an interposer 1055 is attached to a copper heat spreader1060 which is attached to side substrate 1065. It is understood thatinterposer 1055 does not have any TSVs. A secondary flip chip substrate1070 is used to route the signals and supplies from the interposer 1055the side-substrate 1065. In another embodiment, wirebonds are used toconnect the interposer 1055 to the side-substrate 1065 instead ofsecondary flip chip substrates 1070.

FIG. 11 is a cross-section of a substrate connector used to routesignals and supplies over a cavity in accordance with an exemplaryembodiment. Substrate connector 1140 includes an array of fine pitchbumps 1130 and an array of coarse pitch bumps 1120. A gap 1110 betweenthe fine pitch bumps 1130 and the coarse pitch bumps 1120 provides abridge for connecting over a cavity.

FIG. 12 is a cross-section of a substrate connector used to routesignals and supplies over a cavity in accordance with an exemplaryembodiment. Substrate connector 1140 includes a first array of finepitch bumps 1130 and a second array of fine pitch bumps 1150. A gap 1110between the first array of fine pitch bumps 1130 and the second array offine pitch bumps 1150 provides a bridge for connecting over a cavity.

FIG. 13A is a bump joint assembly between two substrates according toprior art. Substrate 1320 and substrate 1310 are connected using bump1330. FIG. 13B is a bump joint assembly between a substrate and a dieaccording to prior art. Substrate 1320 and die 1340 are connected usingbump 1330. FIG. 13C is a bump joint assembly between two die accordingto prior art. Die 1340 and die 1350 are connected using bump 1330.

FIG. 14 is a top view of a landing pad used to connect components, andside view of a plurality of holes shape and depth used to enforce aconnection between components in accordance with an exemplaryembodiment. Landing pad 1410 includes a hole 1420. Landing pad 1410 canalso include a hole 1430 that has a different shape and depth than hole1420. Similarly, landing pad 1410 can have a hole 1440 that has adifferent shape and depth than holes 1420 and 1430.

FIG. 15A is a top view of a plurality of holes with uniform pitch, shapeand depth in accordance with an exemplary embodiment. Landing pad 1510includes an array of holes 1515, each having the same pitch, shape, anddepth.

FIG. 15B is a top view of a plurality of holes with varying pitch, shapeand depth in accordance with an exemplary embodiment. Landing pad 1520includes an array of holes, including holes 1530, 1540, 1550 and 1560having varying pitch, shape, and depth.

FIG. 16 illustrates an assembly process used to assemble mask definedcomponents and substrates without under bump metallization (UBM) inaccordance with an exemplary embodiment. Components 1610 and 1620 areassembled using bumps 1630 and 1640 and spaced apart by spacers 1660.The bumps 1630 and 1640 are placed partially inside a through hole withproper depth. After process reflow, the bumps 1630 and 1640 are meltedand joined together to form a connection 1670 between the components1610 and 1620.

FIG. 17 illustrates an assembly process used to assemble mask definedcomponents and substrates in accordance with an exemplary embodiment.Components 1710 and 1720 are assembled together using bumps 1730 and1740. Conductive material 1750 partially fills a mask defined hole.After a reflow the bumps 1730 and 1740 are melted and joined together toform a connection between components 1710 and 1720.

FIG. 18A illustrates a plurality of wirebonded dies placed inside asubstrate cavity in accordance with an exemplary embodiment. Assembly1810 includes a substrate 1820 with a cavity 1825 created therein.Devices 1830 and 1835 are wirebonded 1840 to substrate 1820.

FIG. 18B illustrates a plurality of wirebonded dies placed on a copperheat spreader in accordance with an exemplary embodiment. In assembly1850, devices 1860 and 1865 are placed on a copper heat spreader 1855(or substrate) and wirebonded 1885 to substrate 1870. A substrate 1875is assembled to substrate 1870 using bumps 1880.

FIG. 19A illustrates a plurality of wirebonded dies placed side by sideinside a substrate cavity in accordance with an exemplary embodiment.Assembly 1910 includes a stack of assemblies having a substrate 1915with a cavity 1920 created therein. Multiple devices 1925 can be placedin the cavity 1920 and wirebonded 1930 to the substrate 1915. Assembliesare stacked and separated using bumps 1935.

FIG. 19B illustrates a plurality of wirebonded dies placed inside asubstrate cavity side by side and on top of each other in accordancewith an exemplary embodiment. Assembly 1940 is similar to assembly 1910,except multiple devices 1945 are placed on top of one another within thesubstrate cavity.

FIG. 19C illustrates a plurality of wirebonded dies placed side by sideinside substrate cavities in accordance with an exemplary embodiment.Assembly 1950 comprises multiple stacked assemblies, each including asubstrate having multiple cavities created therein. Devices are placedside by side within the cavities and are wirebonded to the substrate.

FIG. 19D illustrates a plurality of wirebonded dies placed side by sideand on top of each other inside substrate cavities in accordance with anexemplary embodiment. Assembly 1960 comprises multiple stackedassemblies and is similar to assembly 1950 except multiple devices areplaced on top of one another within the substrate cavities.

It is also understood that the examples and embodiments described hereinare for illustrative purposes only and that various modifications orchanges in light thereof will be suggested to persons skilled in the artand are to be included within the spirit and purview of this applicationand scope of the appended claims.

Having disclosed several embodiments, it will be recognized by those ofskill in the art that various modifications, alternative constructions,and equivalents may be used without departing from the spirit of thedisclosed embodiments. Additionally, a number of well-known processesand elements have not been described to avoid unnecessarily obscuringthe embodiments described herein. Accordingly, the above descriptionshould not be taken as limiting the scope of the claims.

Where a range of values is provided, it is understood that eachintervening value, to the tenth of the unit of the lower limit unlessthe context clearly dictates otherwise, between the upper and lowerlimits of that range is also specifically disclosed. Each smaller rangebetween any stated value or intervening value in a stated range and anyother stated or intervening value in that stated range is encompassed.The upper and lower limits of these smaller ranges may independently beincluded or excluded in the range, and each range where either, neitheror both limits are included in the smaller ranges is also encompassedwithin the embodiments described, subject to any specifically excludedlimit in the stated range. Where the stated range includes one or bothof the limits, ranges excluding either or both of those included limitsare also included.

As used herein and in the appended claims, the singular forms “a”, “an”,and “the” include plural referents unless the context clearly dictatesotherwise. Thus, for example, reference to “a process” includes aplurality of such processes and reference to “the dielectric material”includes reference to one or more dielectric materials and equivalentsthereof known to those skilled in the art, and so forth.

Also, the words “comprise,” “comprising,” “include,” “including,” and“includes” when used in this specification and in the following claimsare intended to specify the presence of stated features, integers,components, or steps, but they do not preclude the presence or additionof one or more other features, integers, components, steps, acts, orgroups.

What is claimed is:
 1. An integrated circuit package comprising: one ormore component(s); and one or more substrate(s), wherein said one ormore substrate(s) including a first substrate and a second substrate,said first substrate including a first surface of said first substrateand a second surface of said first substrate, said second substrateincluding a first surface of said second substrate and a second surfaceof said second substrate, said first substrate including a firstfirst-substrate cavity on the first surface of said first substrate,said second substrate includes a first second-substrate cavity on thefirst surface of said second substrate, said second surface of saidfirst substrate and said second surface of said second substrate islocated between said first surface of said first substrate and the firstsurface of said second substrate, and said one or more component(s)is/are disposed inside said first first-substrate cavity of firstsubstrate and/or said first second-substrate cavity of second substrate.2. The integrated circuit package according to claim 1, wherein one ofsaid one or more component(s) is electrically and/or optically coupledto said one or more substrate(s) using a flip chip or a wirebond methodor a waveguide.
 3. The integrated circuit package according to claim 1,wherein said one or more substrate(s) comprises of waveguide(s) and/ornanowires.
 4. The integrated circuit package according to claim 1,wherein one of said one or more component(s) is a powermanagement/regulator or power device or security sub-circuit or tamperdetect circuit or router or switch or antenna or radar or phased arrayor modem or baseband or transceiver or mm-wave subsystem orsilicon-on-insulator or amplifier or Field Programmable Gate Array(FPGA) or capacitor or resistor or inductor or processor or memory orsensor or analog-to-digital converter or digital-to-analog converter orelectrical-optical converter or optical-electrical converter or LightEmitting Diode (LED) or micro LED or Application-Specific IntegratedCircuit (ASIC) or Through-Silicon Via (TSV) or laser or analog circuitor digital circuit or Serializer/Deserializer (SerDes) or filter or Lensor Graphics Processing Unit (GPU) or magnet or waveguide or wirebond orepoxy mold compound (EMC) or under-fill material or heat-pipe or mirroror fan or bump or fiber or accelerator/co-processor or processor core ornanowire or Microelectromechanical Systems (MEMS) or membrane or heatspreader or energy source or sensing material or piezoelectric or lightsource or touch screen or display or Liquid Crystal Display (LCD) ororganic light-emitting diode (OLED) or battery or Electromagnetic Shield(EMI) coating.
 5. The integrated circuit package according to claim 1,wherein one of said one or more component(s) is/are stackedcomponent(s).
 6. The integrated circuit package according to claim 1,wherein one of said one or more substrate(s) is a semiconductor.
 7. Anintegrated circuit package comprising: one or more component(s); and oneor more substrate(s), wherein said one or more substrate(s) including afirst substrate and a second substrate, said first substrate including afirst surface of said first substrate and a second surface of said firstsubstrate, said second substrate including a first surface of saidsecond substrate and a second surface of said second substrate, saidfirst substrate including a first first-substrate cavity on the firstsurface of said first substrate, said second substrate includes a firstsecond-substrate cavity on the first surface of said second substrate,said first surface of said first substrate and the first surface of saidsecond substrate is located between said second surface of said firstsubstrate and said second surface of said second substrate, and said oneor more component(s) is/are disposed inside said first first-substratecavity of first substrate and/or said first second-substrate cavity ofsecond substrate.
 8. The integrated circuit package according to claim7, wherein one of said one or more component(s) is electrically and/oroptically coupled to said one or more substrate(s) using a flip chip ora wirebond method or a waveguide.
 9. The integrated circuit packageaccording to claim 7, wherein said one or more substrate(s) comprises ofwaveguide(s) and/or nanowires.
 10. The integrated circuit packageaccording to claim 7, wherein one of said one or more component(s) is apower management/regulator or power device or security sub-circuit ortamper detect circuit or router or switch or antenna or radar or phasedarray or modem or baseband or transceiver or mm-wave subsystem orsilicon-on-insulator or amplifier or Field Programmable Gate Array(FPGA) or capacitor or resistor or inductor or processor or memory orsensor or analog-to-digital converter or digital-to-analog converter orelectrical-optical converter or optical-electrical converter or LightEmitting Diode (LED) or micro LED or Application-Specific IntegratedCircuit (ASIC) or Through-Silicon Via (TSV) or laser or analog circuitor digital circuit or Serializer/Deserializer (SerDes) or filter or Lensor Graphics Processing Unit (GPU) or magnet or waveguide or wirebond orepoxy mold compound (EMC) or under-fill material or heat-pipe or mirroror fan or bump or fiber or accelerator/co-processor or processor core ornanowire or Microelectromechanical Systems (MEMS) or membrane or heatspreader or energy source or sensing material or piezoelectric or lightsource or touch screen or display or Liquid Crystal Display (LCD) ororganic light-emitting diode (OLED) or battery or Electromagnetic Shield(EMI) coating.
 11. The integrated circuit package according to claim 7,wherein one of said component(s) is/are stacked component(s).
 12. Theintegrated circuit package according to claim 7, wherein one of said oneor more substrate(s) is a semiconductor.
 13. An integrated circuitpackage comprising: one or more component(s); and one or moresubstrate(s), wherein said one or more substrate(s) including a firstsubstrate, a second substrate and a third substrate, wherein said firstsubstrate including a first surface of said first substrate and a secondsurface of said first substrate, said second substrate including a firstsurface of said second substrate and a second surface of said secondsubstrate, said first substrate including a first first-substrate cavityon the first surface of said first substrate, said second substrateincludes a first second-substrate cavity on the first surface of saidsecond substrate, said first surface of said first substrate and thefirst surface of said second substrate is located between said secondsurface of said first substrate and said second surface of said secondsubstrate, said third substrate is coupled to said first substrateand/or said second substrate, and said one or more component(s) is/aredisposed inside said first first-substrate cavity of first substrateand/or said first second-substrate cavity of second substrate.
 14. Theintegrated circuit package according to claim 13, wherein one of saidone or more component(s) is electrically and/or optically coupled tosaid one or more substrate(s) using a flip chip or a wirebond method ora waveguide.
 15. The integrated circuit package according to claim 13,wherein said one or more substrate(s) comprises of waveguide(s) and/ornanowires.
 16. The integrated circuit package according to claim 13,wherein one of said one or more substrate(s) is a semiconductor.
 17. Theintegrated circuit package according to claim 13, wherein one of saidone or more component(s) is a power management/regulator or power deviceor security sub-circuit or tamper detect circuit or router or switch orantenna or radar or phased array or modem or baseband or transceiver ormm-wave subsystem or silicon-on-insulator or amplifier or FieldProgrammable Gate Array (FPGA) or capacitor or resistor or inductor orprocessor or memory or sensor or analog-to-digital converter ordigital-to-analog converter or electrical-optical converter oroptical-electrical converter or Light Emitting Diode (LED) or micro LEDor Application-Specific Integrated Circuit (ASIC) or Through-Silicon Via(TSV) or laser or analog circuit or digital circuit orSerializer/Deserializer (SerDes) or filter or Lens or GraphicsProcessing Unit (GPU) or magnet or waveguide or wirebond or epoxy moldcompound (EMC) or under-fill material or heat-pipe or mirror or fan orbump or fiber or accelerator/co-processor or processor core or nanowireor Microelectromechanical Systems (MEMS) or membrane or heat spreader orenergy source or sensing material or piezoelectric or light source ortouch screen or display or Liquid Crystal Display (LCD) or organiclight-emitting diode (OLED) or battery or Electromagnetic Shield (EMI)coating.
 18. The integrated circuit package according to claim 13,wherein one of said component(s) is/are stacked component(s).
 19. Theintegrated circuit package according to claim 13, wherein one or morenanowire is coupled to said component(s) and/or said substrate(s) and/orsaid cavity(ies).
 20. The integrated circuit package according to claim7, wherein one or more nanowire is coupled to said component(s) and/orsaid substrate(s) and/or said cavity(ies).